# Quartus-compatible Tcl script to generate a Verilog file with compile time

# Get the project directory (Quartus sets this as the working directory)
set project_dir [pwd]

# Define the output Verilog file path relative to project directory
set filename "../src/compile_time.v"

# Build the full file path
set full_path [file normalize [file join $project_dir $filename]]

# Get current time, formatted as "YYYY-MM-DD HH:MM:SS"
set current_time [clock format [clock seconds] -format "%Y-%m-%d %H:%M:%S"]

# Define the Verilog module content, escaping special characters
set verilog_content "reg \[255:0\] compile_time_buff = \" Build_time: $current_time\"/*synthesis noprune*/;\n\n"

# Write to the file (overwrite mode)
if {[catch {set file_handle [open $full_path w]} error_msg]} {
    error "Could not open file '$full_path' for writing: $error_msg"
}
puts $file_handle $verilog_content
close $file_handle

puts "Successfully wrote '$full_path' with current build time: $current_time"